1. Field of the Invention
This invention relates to a pulse counter circuit adapted to perform precision counting operations, and a pulse signal changeover circuit suitable for use in the pulse counter circuit.
2. Prior Art
Conventionally, there are known circuits which perform various operations based on counted pulses. Such circuits include a PWM (Pulse Width Modulation) circuit, of which a typical construction is shown in FIG. 1. In the figure, reference numeral 1 designates a clock generator for generating a master clock signal .phi..sub.0 having a predetermined repetition period. Reference numeral 5 shows a counter which is capable of counting binary data of "n" bits. The count B of the counter 5 is incremented in synchronism with clock pulses of the master clock signal .phi..sub.0. The counter 5 is provided with a reset terminal R to which is applied a synchronizing pulse signal SYNC. The count B of the counter 5 is cleared to "0" upon a fall of the pulse signal SYNC. Reference numeral 7 designates a register for storing binary data of "n" bits, and a numerical value corresponding to the binary data of "n" bits is delivered as a reference value A.
Reference numeral 4 designates a comparator for comparing the count value B with the reference value A. When the former is equal to the latter, the comparator 4 delivers a signal at a level "1", whereas when the former is not equal to the latter, it delivers a signal at a level "0". Reference numeral 6 designates an R-S flip-flop which has its internal logical state set to "1" when an input signal applied to an input terminal S thereof falls from "1" to "0", and thereby delivers an output signal S.sub.OUT at "1". On the other hand, when an input signal applied to a reset terminal R of the R-S flip-flop 6 falls from "1" to "0", the internal logical state of the R-S flip-flop 6 is reset to "0" to deliver the output signal S.sub.OUT at "0". The R-S flip-flop circuit 6 has its set input terminal S supplied with an output signal (signal S.sub.4) from the comparator 4. The reset input terminals R of the counter 5 and the R-S flip-flop 6 are each supplied with the aforementioned synchronizing pulse signal SYNC the logical state of which is normally "0", and changed to "1" for a very short time period at intervals of a predetermined time period.
Next, the operation of the above PWM circuit will be described with reference to FIG. 2a to FIG. 2d. Let it be assumed that the register 7 has the reference value A stored therein in advance. First, when the synchronizing pulse signal SYNC falls at a time point t.sub.0 as shown in FIG. 2b, the counter 5 and the R-S flip-flop 6 are both reset to "0" as shown in FIG. 2a and FIG. 2d, respectively. Thereafter, as shown in FIG. 2a, the counter 5 counts pulses of the master clock signal .phi..sub.0 to increment the count B as time elapses. When the count B becomes equal to the reference value A one repetition period of the master clock signal .phi..sub.0 earlier than a time point t.sub.50, the logical state of the signal S.sub.4 is changed to "1" as shown in FIG. 2c. However, with a rise of the following clock pulse at the time point t.sub.50, the count B becomes larger than the reference value A as shown in FIG. 2a, so that the logical state of the signal S.sub.4 is changed again to "0" (FIG. 2c). In synchronism with this change of the logical state of the signal S.sub.4 from "1" to "0", the R-S flip flop 6 has its internal logical state set to "1" whereby the output signal S.sub.OUT is changed to "1" (FIG. 2d).
Next, when the synchronizing pulse signal SYNC falls again, as shown in FIG. 2b, at a time point t.sub.100 subsequent to a rise thereof, the counter 5 and the R-S flip-flop 6 are both reset to "0" to clear the count B of the counter 5 to 0 (FIG. 2a) and set the logical state of the output signal S.sub.OUT from the flip-flop 6 to "0". Thereafter, the same operations are repeatedly carried out. According to the above construction of the PWM circuit, it is possible to set the timing of a rise of the output signal S.sub.OUT (time point t.sub.50, time point t.sub.150, . . . ) as desired by the use of the reference value A, with the timing of a fall of same (time point t.sub.0, time point t.sub.100, time point t.sub.200, . . . ) being fixed by the synchronizing pulse signal SYNC. That is, the reference value A can be set to a desired value according to a desired duty ratio, whereby the output signal S.sub.OUT can be subjected to pulse width modulation.
According to the above construction of the PWM circuit, however, the time resolution of the output signal S.sub.OUT is limited by the frequency of the master clock signal .phi..sub.0. In other words, to enhance the time resolution of the output signal S.sub.OUT, there has been no other method than a method of generating a signal having a frequency higher than that of the master clock signal .phi..sub.0 by the use of a frequency synthesizer or the like, to be supplied to the counter 5. However, the use of a frequency synthesizer not only makes the PWM circuit complicated in construction and difficult to handle but also requires an increased manufacturing cost.